1. Field of the Invention
The present invention relates generally to fabrication of insulated gate field effect transistors (MOSFETs), and, more particularly, to MOSFETs that are formed on an insulating substrate.
2. Related technology
MOSFETs are a common component of integrated circuits (ICs). FIG. 1 shows a cross sectional view of a conventional MOSFET device. The MOSFET is fabricated on a bulk silicon substrate 10 within an active region bounded by shallow trench isolations 12 that electrically isolate the active region of the MOSFET from other IC components fabricated on the substrate 10. The MOSFET is comprised of a gate 14 and a channel region 16 that are separated by a thin gate insulator 18 such as silicon oxide or silicon oxynitride. The gate 14 is typically formed of a heavily doped semiconductor material such as polysilicon. The source and drain regions of the MOSFET comprise shallow source and drain regions 24 and deep source and drain regions 20 formed on opposing sides of the channel region 16. The shallow source and drain regions 24 are implanted after the formation of a protective layer 26 over the substrate. Deep source and drain regions 20 are then formed by ion implantation after formation of a spacer 22 around the gate 14. Source and drain suicides 28 are formed on the deep source and drain regions 20 to provide ohmic contacts and reduce contact resistance. The silicides 28 are comprised of the substrate semiconductor material and a metal such as cobalt (Co) or nickel (Ni). A silicide 30 is also formed at the upper surface of the gate 14.
An alternative to the formation of devices on bulk semiconductor substrates is semiconductor on insulator (SOI) construction. In SOI construction, MOSFETs are formed on a substrate that includes a layer of a dielectric material beneath the MOSFET active regions. SOI devices have a number of advantages over devices formed in a bulk semiconductor substrate, such as better isolation between devices, reduced leakage current, reduced latch-up between CMOS elements, reduced chip capacitance, and reduction or elimination of short channel coupling between source and drain regions. FIG. 2 shows an example of a conventional fully depleted SOI MOSFET. The SOI MOSFET is formed on an SOI substrate comprised of a silicon layer 32 and a dielectric layer 34. The MOSFET structure is formed on an isolated region 36 of a silicon layer that has been etched to define individual islands on which individual devices are formed. A thin undoped channel region 16 is located at the center of the silicon region 36. Source and drain extensions 24 are implanted into the silicon region 36 at opposing sides of a gate 14 formed on a gate insulator 18. Following formation of a spacer 22, elevated source and drain regions 38 are grown on the silicon region 38, and silicide source and drain contacts 28 and a silicide gate contact 30 are then formed.
One option for enhancing MOSFET performance is to increase the carrier mobility of the MOSFET semiconductor material so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of increasing carrier mobility that has become a focus of recent attention is the use of silicon material to which strain is applied. Tensile strained silicon may be formed by growing an epitaxial layer of semiconductor on a silicon germanium substrate. The silicon germanium lattice has a slightly larger lattice constant than a pure silicon lattice due to the presence of the larger germanium atoms in the lattice. Since the epitaxially grown silicon aligns itself to the silicon germanium lattice, a tensile strain is created in the silicon lattice. A moderate tensile strain increases electron mobility, and a more substantial tensile strain increases hole mobility. The amount of tensile strain increases with the proportion of germanium in the silicon germanium lattice. It has also been found that a moderate compressive strain improves hole mobility.
An example of a MOSFET incorporating a tensile strained silicon layer is shown in FIG. 3. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 32 grown on a silicon layer 10. The silicon germanium layer is typically a graded layer in which the germanium content is gradually increased from zero to between 10% to 40%, depending on the amount of strain that is desired. An epitaxial layer of strained silicon 34 is grown on the silicon germanium layer 32. The MOSFET uses conventional MOSFET structures including deep source and drain regions 20, shallow source and drain extensions 24, a gate oxide layer 18, a gate 14 surrounded by a protective layer 26, a spacer 22, source and drain suicides 28, a gate silicide 30, and shallow trench isolations 12. The strained silicon material in the channel region 16 provides enhanced carrier mobility between the source and drain.
Strained silicon may also be incorporated into a MOSFET formed on an SOI substrate. FIG. 4 shows an example of a strained silicon SOI MOSFET. In this device, the MOSFET is formed on an SOI substrate that comprises a silicon germanium layer that overlies a dielectric layer 40. The silicon germanium layer is patterned to define isolated regions 42 on which individual MOSFETs are formed. A strained silicon layer 44 is grown on the silicon germanium region 42. The MOSFET is then formed in a manner similar to that of the conventional strained silicon device of FIG. 3.
It is difficult to form a fully depleted SOI device that incorporates a strained silicon channel. To control the short channel effect, a fully depleted SOI MOSFET preferably has a channel region thickness that is no more than approximately one third of the channel length. However, given the need to provide a supporting layer of silicon germanium beneath the strained silicon channel, the total channel thickness becomes a limitation on channel length, or else the thickness of strained silicon is not sufficient to provide significant mobility enhancement.
Other considerations present further obstacles for miniaturization of SOI devices generally. In conventional fully depleted SOI devices, it is typical to produce a very thin channel layer by performing chemical mechanical polishing (CMP) on the substrate until a desired thickness of semiconductor material remains. However, CMP produces a non-uniform surface that can have a variance in thickness of as much as 100 Å. As critical dimensions are reduced, such variability in thickness becomes unacceptable. For example, for a 45 nm device, a channel region thickness of approximately 150 Å is desirable. Given the thickness variability of polished layers, it is very difficult to reliably produce channel layers having the correct thickness at these dimensions.
It would be desirable to grow a layer of semiconductor material on a dielectric material in order to achieve an essentially uniform channel region thickness. However, conventional semiconductor device production techniques rely on the use of crystal lattices as templates for the growth of additional crystalline material. For example, silicon wafers are constituted of single crystal silicon that is cut along one of the crystal faces to provide a regular crystal lattice. This lattice serves as a template to which deposited atoms of silicon or other elements having the same lattice structure will align upon deposition, thus forming additional single crystal material. In the absence of such a template, deposited silicon takes the form of polycrystalline silicon or amorphous silicon, which is composed of individual grains each having a crystal lattice that is randomly oriented with respect to those of the surrounding grains. These forms of silicon exhibit poor conductivity compared to single crystal silicon and therefore are not desirable for use in the active regions of MOSFETs. Therefore, to date it has generally not been possible to grow single crystal silicon on other materials, particularly conventional dielectrics such as silicon oxide and silicon oxynitride, whose structures are essentially amorphous or do not match the silicon lattice.
Therefore the conventional techniques for producing semiconductor on insulator devices are not satisfactory for producing devices having small critical dimensions and devices incorporating strained silicon.